1. Field of the Invention
The invention relates to an integrated circuit, and in particular to electrostatic discharge (ESD) protection circuits.
2. Description of the Related Art
Integrated circuits (IC) utilize input/output (I/O) drivers to interface with external circuitry and data connections, there exists an increasing demand for I/O drivers which can tolerate high drain and gate voltages without incurring hot carrier or gate oxide degradation. The scaling of gate oxides in deep sub-micron technologies in combination with customer demands for mixed voltage product applications has forced designers to create I/O drivers which meet requirements.
Integrated circuits comprise semiconductor devices that are susceptible to damage from electrical overstress conditions (EOS), including electrostatic discharge (ESD), transient conditions, latch-up, incorrect polarity connections. The electrical overstress conditions are characterized by over-voltage and over-current stress events. Electrostatic charge (ESC) can accumulate in a body and damage semiconductor devices and circuitry therein if the body is brought into contact with the ICs. Thus efforts have been put though to protect semiconductor devices from electrostatic discharge and other electrical overstress conditions.
FIG. 1 is a circuit schematic of a conventional electrostatic discharge protection circuitry in an integrated circuit, comprising PMOS transistor M10, NMOS transistors M12 and M14, and resistor R10.
NMOS transistors stacked in a cascade configuration provide robust ESD protection for mixed voltage I/O in semiconductor technologies. Stacked NMOS M12 and M14 provide ESD protection to internal components of the integrated circuit to prevent from exposure to excessive currents in an ESD event. The stacked NMOS configuration also protects the integrated circuit from excessive currents in transient condition during normal operation. However, this kind of device has high snapback voltage. Also, the high snapback voltage of the stacked NMOS degrades second breakdown trigger current IT2 since the power dissipation is great, resulting in poor ESD performance in the stacked NMOS circuit configuration. Thus a need exists for ESD protection in high voltage tolerant I/O.